0 votes
in Verilog by (220 points)

How do I code a multiplexer in Verilog?

2 Answers

0 votes
by (240 points)

Here are some examples:


assign q = sel == 0 ? in0 : (sel == 1 ? in1 : (sel == 2 ? in2 : in3));
always @(*) begin
case (sel)
0: q = in0;
1: q = in1;
2: q = in2;
3: q = in3;
always @(*) begin
if (sel == 0) q = in0;
else if (sel == 1) q = in1;
else if (sel == 2) q = in2;
else q = in3;
0 votes
by (200 points)

A multiplexer has multiple inputs and a single output. A select signal is used to determine which one of the multiple inputs will appear on the output.

One way to code a 4 to 1 multiplexer is shown below (https://www.chipverify.com/verilog/verilog-4to1-mux):

module mux_4to1_assign ( input [3:0] a, // 4-bit input called a 
input [3:0] b, // 4-bit input called b
input [3:0] c, // 4-bit input called c
input [3:0] d, // 4-bit input called d
input [1:0] sel, // input sel used to select between a,b,c,d
output [3:0] out); // 4-bit output based on input sel

// When sel[1] is 0, (sel[0]? b:a) is selected and when sel[1] is 1, (sel[0] ? d:c) is taken
// When sel[0] is 0, a is sent to output, else b and when sel[0] is 0, c is sent to output, else d
assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a);

Four-bit inputs, a,b,c and d are defined. Output variable 'out' is also 4-bit. The select signal is defined as a 2-bit signal. The value of the select signal decides which of the four inputs appear on the output. When 'sel' is 00, 'a' is sent to output, when it is 01, 'b' is sent to the output. Similarly, when 'sel' is 10, 'c' is sent to output and when it is 11, 'd' is sent to the output.
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