Verilog Wait?

Question

What is wait in Verilog and how do I use it?

Answer 1

A wait statement is a form of the event control. It is used to delay an execution of a procedural statement until some condition becomes true. The nature of the wait statement is level-sensitive.

Syntax:

wait_statement ::= wait ( expression ) statement_or_null;

begin
    wait  (enable)
    #10 c = 1'b1; 
    #10 c = 1'b0; 
end

Answer 2

As the name shows,with the wait statement, the prorgram will wait until a statement becomes true. For example:

 wait (request==1)
 out<= in_data;

It will wait until request becomes one and then sends the input data to the output.