0 votes
in Verilog by (220 points)

How do you use integers in Verilog?

2 Answers

0 votes
by (240 points)

If you are asking about variables of the integer data type I use:

- for loop variables of for loops,
- implicitly as a localparams and parameters - for ranges, borders, settings etc

If you are asking about integer literals then I use it as integer literals (or constants as its named in the Verilog standard) - in expressions and equations. I use it in various formats: decimal (just 113 for example), based (2'b01, 3'd7, 16'h0123) which is composed of up to three tokens - an optional size constant, an apostrophe character (', ASCII 0x27) followed by a base format character, and the digits representing the value of the number.

localparam size = 32;
next_addr = addr + 16'h24;
case (x)
3'b001: ...
3'b010: ...
0 votes
by (300 points)

The "int" is used for 32-bit integer data types. However "shortint" and "longint" will also be used as integer but for 16 and 64 bit respectively. All of these are signed integers.

Hardware Coder Community

© 2022 by Hardware Coder. User contributions are licensed under cc by-sa 4.0 with attribution required. Attribution means a link to the question, answer, user, etc on this site.

This site is owned and operated by Hardware Coder in McKinney, Texas.

Send Us A Message
About Us

By using this site, you agree to the following:

Privacy Policy
Terms and Conditions
DMCA Policy
Earnings Disclaimer
Legal Disclaimer