JK Flip Flop Verilog?

Question

How do I implement a JK flip flop in Verilog?

Answer 1

Here's an example:

module jkfflop (
  input j,
  input k,
  input clk,
  output q,
  output qn
);

  reg ff;

  always @(posedge clk) begin
    case({j,k})
      {1'b0,1'b0}: ff <= ff;
      {1'b0,1'b1}: ff <= 1'b0;
      {1'b1,1'b0}: ff <= 1'b1;
      {1'b1,1'b1}: ff <= ~ff;
    endcase
  end

  assign q = ff;
  assign qn = ~ff;

endmodule

Answer 2

Module JKFF (input reset, clk, J, K, output Q)

 always @(posedge clk, posedge rst) begin 

 if (reset) 
  Q <= 1'b0;
 else 
  case({j,k})
  2'b00:  Q <= Q;
  2'b01:  Q <= 0;
  2'b00:  Q <= 1;
  2'b00:  Q <=~Q;
  default Q <= Q;
  endcase
 end
endmodule